A) Field of the Invention
The present invention relates to a thyristor and more particularly to an insulated gate type thyristor having an insulated gate.
B) Description of the Related Art
A thyristor having a pnpn lamination structure is known as a switching device having a low on-resistance. The pnpn lamination structure is understood as a structure merging a pnp bipolar junction transistor and an npn bipolar junction transistor. As a high voltage is applied between anode-cathode and a forward bias is applied to a p-type base or an n-type base, one bipolar junction transistor turns on to forward-bias the other base. The other bipolar junction transistor also turns on thereafter. Positive feedback is mutually applied to both bipolar transistors to enter a latch-up state. In this way, a low on-resistance can be realized. As the polarity of the voltage between anode-cathode is reversed, the thyristor turns off.
A gate turn-off thyristor (GTO) is a thyristor which can turn off, without reversing the polarity of voltage between anode-cathode, for example, by backward-biasing gate-cathode to pull the drain carriers in the base region through the gate electrode. Since large current flows, a proper gate drive circuit is required to be prepared.
A thyristor called an insulated gate transistor is also known (B. J. Baliga: IEEE Trans. El. Dev. ED-31, No. 6, 821, 1984). The npn portion of a pnpn thyristor structure is formed in a planar transistor structure, and an insulated gate electrode is formed on a region traversing an n-type emitter region and a p-type base region and reaching an n-type base region. A positive polarity bias voltage is applied to the insulated gate electrode to form an inversion layer in a surface layer of the p-type base region, to connect the n-type emitter region and n-type base region, to inject carriers (electrons) into the n-type base region, and to turn on the thyristor. Gate turn-off is also possible.
Instead of the planar structure, another structure has also been proposed in which an insulated gate electrode is formed in a trench formed by passing through the p-type base region from the surface of the n-type region of a pnpn lamination structure and entering the n-type base region (e.g., JP-A-2000-311998).